Zero-Skew Clock Routing Trees With Minimum Wirelength
نویسندگان
چکیده
In the design of high performance VLSI systems, minimization of clock skew is an increasingly important objective. Additionally, wirelength of clock routing trees should be minimized in order to reduce system power requirements and deformation of the clock pulse at the synchronizing elements of the system. In this paper, we present the Deferred-Merge Embedding (DME) algorithm, which in linear time embeds any given connection topology into the Manhattan plane to create a clock tree with zero skew while minimizing total wirelength. Extensive experimental results show that the algorithm yields exact zero skew trees with 9% to 16% wirelength reduction over previous constructions [5] [6]. The DME algorithm may be applied to either the Elmore or the linear delay model, and yields optimal total wirelength for linear delay.
منابع مشابه
Minimum Wirelength Zero Skew Clock Routing Trees with Buffer Insertion
Zero skew clock routing is an issue of increasing importance in the realm of VLSI design. As a result of the increasing speeds of on-chip clocks, zero skew clock tree construction has become critical for the correct operation of high performance VLSI circuits. In addition, in an effort to both reduce power consumption and the deformation of clock signals at synchronizing elements on a chip, a m...
متن کاملA Simple Yet Effective Merging Scheme for Prescribed-Skew Clock Routing
In order to achieve multi-GHz operation frequency for VLSI design, clock networks need to be designed in a very elaborated manner and be able to deliver prescribed useful skews rather than merely zero-skew. Although traditional zero-skew clock routing methods can be extended directly to prescribed skews, they tend to result in excessive wirelength as the differences among delay-targets for cloc...
متن کامل5 Conclusions and Directions for Future Work 4 Experimental Results
In the design of high performance VLSI systems, minimization of clock skew is an increasingly important objective. Additionally, wirelength of clock routing trees should be minimized in order to reduce system power requirements and deformation of the clock pulse at the synchronizing elements of the system. In this paper, we rst present the Deferred-Merge Embedding (DME) algorithm, which embeds ...
متن کاملMatching-based methods for high-performance clock routing
Minimizing clock skew is important in the design of high performance VLSI systems. We present a general clock routing scheme that achieves very small clock skews while still using a reasonable amount of wirelength. Our routing solution is based on the construction of a binary tree using geometric matching. For cell-based designs, the total wirelength of our clock routing tree is on average with...
متن کاملHigh Performance Buffered X-architecture Zero-skew Clock Tree Construction with via Delay Consideration
As VLSI technology advances into nanometer dimensions, clock routing becomes a limiting factor in determining chip performance. To deal with the challenge, X-architecture has been proposed and widely applied in routing field because it contributes more improvements in terms of the clock delay, wirelength, and power consumption than general Manhattan-architecture. This work proposes an X-archite...
متن کامل